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1 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c 4m-bit [512k x 8] cmos single voltage 3v only equal sector flash memory features ? extended single - supply voltage range 2.7v to 3.6v ? 524,288 x 8 only ? single power supply operation - 3.0v only operation for read, erase and program operation ? fully compatible with mx29lv040 device ? fast access time: 55r/70/90ns ? low power consumption - 30ma maximum active current - 0.2ua typical standby current ? command register architecture - 8 equal sector of 64k-byte each - byte programming (9us typical) - sector erase (sector structure 64k-byte x8) ? auto erase (chip & sector) and auto program - automatically erase any combination of sectors with erase suspend capability - automatically program and verify data at specified address ? erase suspend/erase resume - suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase ? status reply - data# polling & toggle bit for detection of program and erase operation completion ? sector protection - hardware method to disable any combination of sectors from program or erase operations - any combination of sectors can be erased with erase suspend/resume function ? cfi (common flash interface) compliant - flash device parameters stored on the device and provide the host system to access ? 100,000 minimum erase/program cycles ? latch-up protected to 100ma from -1v to vcc+1v ? package type: - 32-pin plcc - 32-pin tsop - all pb-free devices are rohs compliant
2 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c pin configurations 32 plcc 32 tsop (standard type) (8mm x 20mm) symbol pin name a0~a18 address input q0~q7 data input/output ce# chip enable input we# write enable input oe# output enable input gnd ground pin vcc +3.0v single power supply pin description 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe# a10 ce# q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd q3 q4 q5 q6 a12 a15 a16 a18 vcc we# a17 mx29lv040c a11 a9 a8 a13 a14 a17 we# vcc a18 a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mx29lv040c
3 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q7 a0-a18 ce# oe# we#
4 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c table 1. sector (group) structure sector a18 a17 a16 address range sa0 0 0 0 00000h-0ffffh sa1 0 0 1 10000h-1ffffh sa2 0 1 0 20000h-2ffffh sa3 0 1 1 30000h-3ffffh sa4 1 0 0 40000h-4ffffh sa5 1 0 1 50000h-5ffffh sa6 1 1 0 60000h-6ffffh sa7 1 1 1 70000h-7ffffh note:all sectors are 64 kbytes in size.
5 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c table 2. bus operation--1 operation ce# oe# we# address q0~q7 read mode l l h ain dout write l h l ain din standby mode vcc 0.3v x x x high-z output disable l h h x high-z bus operation--2 operation ce# oe# we# a0 a1 a6 a9 q0~q7 read silicon id l l h l l x vhv c2h manufactures code read silicon id l l h h l x vhv 4fh device code sector protect l vhv l x x l vhv x chip unprotected l vhv l x x h vhv x sector protect verify l l h x h x vhv co de(1) notes: 1. sector unprotected code:00h. sector protected code:01h. 2. am: msb of address. 3. sector addresses: a18~a16. 4. vhv is 11.5v to 12.5v. 5. x means don't care.
6 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c write commands/command sequences to write a command to the device, system must drive we# and ce# to vil, and oe# to vih. in a command cycle, all address are latched at the later falling edge of ce# and we#, and all data are latched at the earlier rising edge of ce# and we#. figure 1 illustrates the ac timing waveform of a write command, and table 3 defines all the valid command sets of the device. system is not allowed to write invalid commands not defined in this datasheet. writing an invalid command will bring the device to an undefined state. requirements for reading array data read array action is to read the data stored in the array. while the memory device is in powered up or has been reset, it will automatically enter the status of read array. if the microprocessor wants to read the data stored in the array, it has to drive ce# (device enable control pin) and oe# (output control pin) as vil, and input the address of the data to be read into address pin at the same time. after a period of read cycle (tce or taa), the data being read out will be displayed on output pin for microprocessor to access. if ce# or oe# is vih, the output will be in tri-state, and there will be no data displayed on output pin at all. after the memory device completes embedded operation (automatic erase or program), it will automatically return to the status of read array, and the device can read the data in any address in the array. in the process of erasing, if the device receives the erase suspend command, erase operation will be stopped temporarily after a period of time no more than tready1 and the device will return to the status of read array. at this time, the device can read the data stored in any address except the sector being erased in the array. in the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. the device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. in program or erase operation, the programming or erasing failure causes q5 to go high. 2. the device is in auto select mode or cfi mode. in the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data.
7 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c sector protect operation when a sector is protected, program or erase operation will be disabled on that protected sector. mx29lv040c provides a methods for sector protection. the method is asserting vhv on a9 and oe# pins, with a6 and ce# at vil. the protection operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for details. chip unprotect operation mx29lv040c provides one methods for chip unprotect. the chip unprotect operation unprotects all sectors within the device. it is recommended to protect all sectors before activating chip unprotect mode. all sector groups are unpro- tected when shipped from the factory. the method is asserting vhv on a9 and oe# pins, with a6 at vih and ce# at vil (see table 2). the unprotect operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for details. automatic select operation when the device is in read array mode, erase-suspended read array mode or cfi mode, user can issue read silicon id command to enter read silicon id mode. after entering read silicon id mode, user can query several silicon ids continuously and does not need to issue read silicon id mode again. when a0 is low, device will output macronix manufacture id c2. when a0 is high, device will output device id. in read silicon id mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. another way to enter read silicon id is to apply high voltage on a9 pin with ce#, oe#, a6 and a1 at vil. while the high voltage of a9 pin is discharged, device will automatically leave read silicon id mode and go back to read array mode or erase-suspended read array mode. when a0 is low, device will output macronix manufacture id c2. when a0 is high, device will output device id. verify sector protect status operation mx29lv040c provides hardware sector protection against program and erase operation for protected sectors. the sector protect status can be read through sector protect verify command. this method requires vhv on a9 pin, vih on we# and a1 pins, vil on ce#, oe#, a6 and a0 pins, and sector address on a16 to a18 pins. if the read out data is 01h, the designated sector is protected. oppositely, if the read out data is 00h, the designated sector is not protected. data protection to avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. besides, only after successful completion of the specified command sets will the device begin its erase or program operation. other features to protect the data from accidental alternation are described as followed.
8 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c low vcc write inhibit the device refuses to accept any write command when vcc is less than 1.4v. this prevents data from spuriously altered. the device automatically resets itself when vcc is lower than 1.4v and write cycles are ignored until vcc is greater than 1.4v. system must provide proper signals on control pins after vcc is larger than 1.4v to avoid uninten- tional program or erase operation write pulse "glitch" protection ce#, we#, oe# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. logical inhibit a valid write cycle requires both ce# and we# at vil with oe# at vih. write cycle is ignored when either ce# at vih, we# a vih, or oe# at vil. power-up sequence upon power up, mx29lv040c is placed in read array mode. furthermore, program or erase operation will begin only after successful completion of specified command sequences. power-up write inhibit when we#, ce# is held at vil and oe# is held at vih during power up, the device ignores the first command on the rising edge of we#. power supply decoupling a 0.1uf capacitor should be connected between the vcc and gnd to reduce the noise effect.
9 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c table 3. mx29lv040c command definitions silicon id device id protect verify 1st bus cyc addr addr xxx 555 555 555 555 555 555 aa xxx xxx data data f0 aa aa aa aa aa aa 98 b0 30 2nd bus cyc addr 2aa 2aa 2aa 2aa 2aa 2aa data 55 55 55 55 55 55 3rd bus cyc addr 555 555 555 555 555 555 data 90 90 90 a0 80 80 4th bus cyc addr x00 x0 1 (sector) x02 addr 555 555 data c2 4f 00/01 data aa aa 5th bus cyc addr 2aa 2aa data 55 55 6th bus cyc addr 555 sector data 10 30 sector erase cfi read erase suspend erase resume program chip erase automatic select command read mode reset mode notes: 1. it is not allowed to adopt any other code which is not in the above command definition table.
10 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c reset in the following situations, executing reset command will reset device back to read array mode: ? among erase command sequence (before the full command set is completed) ? sector erase time-out period ? erase fail (while q5 is high) ? among program command sequence (before the full command set is completed, erase-suspended program in- cluded) ? program fail (while q5 is high, and erase-suspended program fail is included) ? read silicon id mode ? sector protect verify ? cfi mode while device is at the status of program fail or erase fail (q5 is high), user must issue reset command to reset device back to read array mode. while the device is in read silicon id mode, sector protect verify or cfi mode, user must issue reset command to reset device back to read array mode. when the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command.
11 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c automatic programming the mx29lv040c can provide the user program function by the form of byte-mode. as long as the users enter the right cycle defined in the table.3 (including 2 unlock cycles and a0h), any data user inputs will automatically be pro- grammed into the array. once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. with the internal write state controller, the device requires the user to write the program command and data only. programming will only change the bit status from "1" to "0". that is to say, it is impossible to convert the bit status from "0" to "1" by programming. meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than tready1. when the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. the typical chip program time at room temperature of the mx29lv040c is less than 4.5 seconds. when the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: status q7 q6 q5 in progress*1 q7# to ggling 0 finished q7 stop toggling 0 exceed time limit q7# to ggling 1 *1: the status "in progress" means both program mode and erase-suspended program mode. *2: when an attempt is made to program a protected sector, q7 will output its complement data or q6 continues to toggle for about 1us or less and the device returns to read array state without programing the data in the protected sector.
12 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c sector erase sector erase is to erase all the data in a sector with "1" and "0" as all "1". it requires six command cycles to issue. the first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. after the sector erase command sequence is issued, there is a time- out period of 50us counted internally. during the time-out period, additional sector address and sector erase command can be written multiply. once user enters another sector erase command, the time-out period of 50us is recounted. if user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. the number of sectors could be from one sector to all sectors. after time-out period passing by, additional erase command is not accepted and erase embedded operation begins. during sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. when the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: status q7 q6 q5 q2 in progress 0 toggling 0 toggling finished 1 stop toggling 0 1 exceed time limit 0 to ggling 1 toggling chip erase chip erase is to erase all the data with "1" and "0" as all "1". it needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. during chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too low that chip erase will be interrupted. after chip erase, the chip will return to the state of read array. *1: the status q3 is the time-out period indicator. when q3=0, the device is in time-out period and is acceptible to another sector address to be erased. when q3=1, the device is in erase operation and only erase suspend is valid. *2: when an attempt is made to erase a protected sector, q7 will output its complement data or q6 continues to toggle for 100us or less and the device returned to read array status without erasing the data in the protected sector. when the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: status q7 q6 q5 q3 q2 time-out period 0 to ggling 0 0 toggling in progress 0 toggling 0 1 toggling finished 1 stop toggling 0 1 1 exceed time limit 0 to ggling 1 1 toggling
13 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c when the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon id, sector protect verify, program, cfi query and erase resume. sector erase resume sector erase resume command is valid only when the device is in erase suspend state. after erase resume, user can issue another erase suspend command, but there should be a 400us interval between erase resume and the next erase suspend. if user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. status q7 q6 q5 q3 q2 erase suspend read in erase suspended sector 1 no to ggle 0 n/a to ggle erase suspend read in non-erase suspended sector data data data data data erase suspend program in non-erase suspended sector q7# to ggle 0 n/a n/a sector erase suspend during sector erasure, sector erase suspend is the only valid command. if user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase- suspended read array mode. if user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the tready1 (<=20us) suspend finishes and the device will enter erase-suspended read array mode. user can judge if the device has finished erase suspend through q6, q7, and ry/ by#. after device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of taa; while reading the sector in erase-suspend mode, device will output its status. user can use q6 and q2 to judge the sector is erasing or the erase is suspended.
14 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c table 4-1. cfi mode: identification data values (all values in these tables are in hexadecimal) query command and common flash interface (cfi) mode mx29lv040c features cfi mode. host system can retrieve the operating characteristics, structure and vendor- specified information such as identifying information, memory size, byte/word configuration, operating voltages and timing information of this device by cfi mode. if the system writes the cfi query command "98h", to address "55h"/ "aah" (depending on word/byte mode), the device will enter the cfi query mode, any time the device is ready to read array data. the system can read cfi information at the addresses given in table 4. once user enters cfi query mode, user can not issue any other commands except reset command. the reset command is required to exit cfi mode and go back to the mode before entering cfi. the system can write the cfi query command only when the device is in read mode, erase suspend, standby mode or automatic select mode. table 4-2. cfi mode: system interface data values description address (h) data (h) (byte mode) query-unique ascii string "qry" 10 0051 11 0052 12 0059 primary vendor command set and control interface id code 13 0002 14 0000 address for primary algorithm extended query table 15 0040 16 0000 alternate vendor command set and control interface id code (none) 17 0000 18 0000 address for alternate algorithm extended query table (none) 19 0000 1a 0000 description address (h) data (h) (byte mode) vcc supply minimum program/erase voltage 1b 0027 vcc supply maximum program/erase voltage 1c 0036 vpp supply minimum program/erase voltage 1d 0000 vpp supply maximum program/erase voltage 1e 0000 typical timeout per single word/byte write, 2 n us 1f 0004 typical timeout for maximum-size buffer write, 2 n us 20 0000 typical timeout per individual block erase, 2 n ms 21 000a typical timeout for full chip erase, 2 n ms 22 0000 maximum timeout for word/byte write, 2 n times typical 23 0005 maximum timeout for buffer write, 2 n times typical 24 0000 maximum timeout per individual block erase, 2 n times typical 25 0004 maximum timeout for chip erase, 2 n times typical 26 0000
15 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c table 4-3. cfi mode: device geometry data values description address (h) data (h) (byte mode) device size = 2 n in number of bytes 27 0013 flash device interface description (02=asynchronous x8/x16) 28 0000 29 0000 maximum number of bytes in buffer write = 2 n (not support) 2a 0000 2b 0000 number of erase regions within device 2c 0001 index for erase bank area 1 2d 0007 2e 0000 2f 0000 30 0001 index for erase bank area 2 31 0000 32 0000 33 0000 34 0000 index for erase bank area 3 35 0000 36 0000 37 0000 38 0000 index for erase bank area 4 39 0000 3a 0000 3b 0000 3c 0000
16 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c table 4-4. cfi mode: primary vendor-specific extended query data values description address (h) data (h) (byte mode) query - primary extended table, unique ascii string, pri 40 0050 41 0052 42 0049 major version number, ascii 43 0031 minor version number, ascii 44 0030 unlock recognizes address (0= recognize, 1= don't recognize) 45 0001 erase suspend (2= to both read and program) 46 0002 sector protect (n= # of sectors/group) 47 0001 temporary sector unprotect (1=supported) 48 0001 sector protect/chip unprotect scheme 49 0004 simultaneous r/w operation (0=not supported) 4a 0000 burst mode (0=not supported) 4b 0000 page mode (0=not supported) 4c 0000
17 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c absolute maximum stress ratings surrounding temperature with bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 o c to +125 o c storage temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 o c to +150 o c voltage range vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to +4.0 v a9 and oe#. . . . . . . . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to +12.5 v the other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 v to vcc +0.5 v output short circuit current (less than one second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 ma operating temperature and voltage commercial (c) grade surrounding temperature (t a ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c industrial (i) grade surrounding temperature (t a ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 c to +85 c v cc supply voltages v cc range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 v to 3.6 v
18 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c dc characteristics symbol description min typ max remark iilk input leak 1.0ua iilk9 a9 leak 35ua a9=12.5v iolk output leak 1.0ua icr1 read current(5mhz) 7ma 12ma ce#=vil, oe#=vih icr2 read current(1mhz) 2ma 4ma ce#=vil, oe#=vih icw write current 15ma 30ma ce#=vil, oe#=vih, we#=vil isb standby current 0.2ua 5ua vcc=vcc max, other pin disable isbs sleep mode current 0.2ua 5ua vil input low voltage -0.5v 0.8v vih input high voltage 0.7xvcc vcc+0.3v vhv very high voltage for hardware 11.5v 12.5v protect/unprotect/auto select vol output lo w voltage 0.45v io l=4.0ma voh1 ouput high voltage 0. 85xvcc io h1=-2ma voh2 ouput high vo ltage vcc-0.4v io h2=-100ua
19 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c switching test circuits test condition output load : 1 ttl gate output load capacitance,cl : 30pf(70ns)/100pf(90ns) rise/fall times : 5ns in/out reference levels :1.5v switching test waveforms 1.5v 1.5v test points 3.0v 0.0v output input r1=6.2k ohm r2=2.7k ohm tested device diodes=in3064 or equivalent cl r1 vcc 0.1uf r2 +3.3v
20 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c ac characteristics symbol description min typ max unit taa valid data output after address 55/70/90 ns tce valid data output after ce# low 55/70/90 ns toe valid data output after oe# low 30/30/35 ns tdf data output floating after oe# high 25/25/30 ns toh output hold time from the earliest rising edge of address, 0 ns ce#, oe# trc read period time 55/70/90 ns twc write period time 70/90 ns tcwc command write period time 70/90 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 35/45 ns tdh data hold time 0 ns tvcs vcc se tup time 50 us tcs chip enable setup time 0 ns tch chip enable hold time 0 ns toes output enable setup time 0 ns toeh read 0 ns toeh output enable hold time to ggle & 10 ns data# polling tws we# setup time 0 ns twh we# hold time 0 ns tcep ce# pulse width 35 ns tceph ce# pulse width high 30 ns twp we# pulse width 35 ns twph we# pulse width high 30 ns tghwl read recover time before write 0 ns tghel read recover time before write 0 ns twhwh1 program oper ation 9 us twhwh2 s ector erase operation 0.7 sec tbal s ector add hold time 50 us
21 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 1. command write operation addresses ce# oe# we# din tds ta h data tdh tcs tch tcwc twph tw p toes ta s vih vil vih vil vih vil vih vil vih vil va va: valid address
22 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c read operation figure 2. read timing waveforms addresses ce# oe# ta a we# vih vil vih vil vih vil vih vil voh vol high z high z data valid to e toeh tdf tce tr c outputs to h add valid
23 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c erase/program operation figure 3. automatic chip erase timing waveform tw c address oe# ce# 55h 10h 2aah 555h in progress complete va va ta s ta h tghwl tch tw p tds tdh twhwh2 read status last 2 erase command cycle tcs twph we# data
24 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 4. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no data=ffh ? write data 10h address 555h write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto chip erase completed
25 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 5. automatic sector erase timing waveform tw c address oe# ce# 55h sector address 1 sector address 0 2aah 30h in progress complete va va 30h sector address n ta s ta h tbal tghwl tch tw p tds tdh twhwh2 read status last 2 erase command cycle tcs twph we# data 30h
26 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 6. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data address 555h write data 80h address 555h write data 30h sector address write data address 2aah data# polling algorithm or toggle bit algorithm auto sector erase completed no last sector to erase yes yes no data=ffh
27 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 7. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume
28 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 8. automatic program timing waveforms address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tch tw p tds tdh twhwh1 last 2 read status cycle last 2 program command cycle tcs twph we# data
29 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 9. ce# controlled write timing waveform address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tcep tds tdh twhwh1 or twhwh2 tceph we# data
30 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 10. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes read again data: program data? yes auto program completed data# polling algorithm or toggle bit algorithm next address last byte to be programed no no
31 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c sector protect/chip unprotect figure 11. sector protect/chip unprotect waveform 150us: sector protect 15ms: chip unprotect 1us data sa, a6 a1, a0 ce# we# oe# va va va status va: valid address 40h 60h 60h verification
32 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 12. silicon id read timing waveform ta a tce ta a to e to h to h tdf data o u t c2h 4fh vhv vih vil a9 add ce# a1 oe# we# a0 data o u t data q0-q7 vih vil vih vil vih vil vih vil vih vil vih vil vih vil
33 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c write operation status figure 13. data# polling timing waveforms (during automatic algorithms) tdf tce tch to e toeh to h ce# oe# we# q7 q0-q6 status data status data status data complement true valid data ta a tr c address va va high z high z valid data tr u e
34 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 14. data# polling algorithm read q7~q0 at valid address (note 1) read q7~q0 at valid address start q7 = data# ? q5 = 1 ? q7 = data# ? (note 2) fail pass no no no ye s ye s ye s notes: 1. for programming, valid address means program address. for erasing, valid address means erase sectors address. 2. q7 should be rechecked even q5="1" because q7 may change simultaneously with q5.
35 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 15. toggle bit timing waveforms (during automatic algorithms) tdf tce tch to e toeh ta a tr c to h address ce# oe# we# q6/q2 valid status (first read) valid status (second read) (stops toggling) valid data va va va va : valid address va valid data
36 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c figure 16. toggle bit algorithm notes: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 changes to "1". read q7-q0 twice q5 = 1? read q7~q0 twice pgm/ers fail write reset cmd pgm/ers complete q6 toggle ? q6 toggle ? no (note 1) yes no no yes yes start
37 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a. ac timing at device power-up symbol parameter min. max. unit tvr vcc rise time 20 500000 us/v tr input signal rise ti me 20 us/v tf input signal fall time 20 us/v vcc address ce# we# oe# data tvr taa tr or tf tr or tf tce tf vcc(min) gnd vih vil vih vil vih vil vih vil voh high z vol valid ouput valid address tvcs tr toe tf tr
38 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c min. max. input voltage voltage difference with gnd on all pins except i/o pins -1.0v 12.5v input voltage voltage difference with gnd on all i/o pins -1.0v vcc + 1.0v vcc current -100ma +100ma all pins included except vcc. test conditions: vcc = 3.0v, one pin per testing limits parameter min. typ. max. units chip erase time 4 32 sec sector erase time 0.7 15 sec erase/program cycles 100,000 cycles chip programming time 4.5 13.5 sec byte programming time 9 300 us latch-up characteristics erase and programming performance parameter symbol parameter description test set max unit cin2 control pin capacitance vin=0 12 pf cout o utput capacitance vout=0 12 pf cin input capacitance vin=0 8 pf tsop pin capacitance
39 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c ordering information part no. access operating st andby package remark time(ns) current max.(ma) current max.(ua) MX29LV040CTC-55R 55 30 5 32 pin tsop mx29lv040ctc-70 70 30 5 32 pin tsop mx29lv040ctc-90 90 30 5 32 pin tsop mx29lv040cqc-55r 55 30 5 32 pin plcc mx29lv040cqc-70 70 30 5 32 pin plcc mx29lv040cqc-90 90 30 5 32 pin plcc mx29lv040cti-55r 55 30 5 32 pin tsop mx29lv040cti-70 70 30 5 32 pin tsop mx29lv040cti-90 90 30 5 32 pin tsop mx29lv040cqi-55r 55 30 5 32 pin plcc mx29lv040cqi-70 70 30 5 32 pin plcc mx29lv040cqi-90 90 30 5 32 pin plcc mx29lv040ctc-55q 55 30 5 32 pin tsop pb free mx29lv040ctc-70g 70 30 5 32 pin tsop pb free mx29lv040ctc-90g 90 30 5 32 pin tsop pb free mx29lv040cqc-55q 55 30 5 32 pin plcc pb free mx29lv040cqc-70g 70 30 5 32 pin plcc pb free mx29lv040cqc-90g 90 30 5 32 pin plcc pb free mx29lv040cti-55q 55 30 5 32 pin tsop pb free mx29lv040cti-70g 70 30 5 32 pin tsop pb free mx29lv040cti-90g 90 30 5 32 pin tsop pb free mx29lv040cqi-55q 55 30 5 32 pin plcc pb free mx29lv040cqi-70g 70 30 5 32 pin plcc pb free mx29lv040cqi-90g 90 30 5 32 pin plcc pb free
40 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c part name description mx 29 lv 70 c t c g option: g: lead-free package r: restricted vcc (3.0v~3.6v) q: restricted vcc (3.0v~3.6v) with lead-free package speed: 55: 55ns 70: 70ns 90: 90ns temperature range: c: commercial (0? c to 70? c) i: industrial (-40? c to 85? c) package: q: plcc t: tsop revision: c density & mode: 040: 4m, x8 equal sector type: l, lv: 3v device: 29:flash 040
41 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c package information
42 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c
43 p/n:pm1149 rev. 2.2, jul. 31, 2008 mx29lv040c revision history revision no. description page date 1.0 1. removed "preliminary" p1 jun/30/2005 2. added "recommended operating conditions" p43 1.1 1. modified "low power consumption--active current" from 20ma(max.) p1 a ug/30/2005 to 30ma(max.) 2. added description about pb-free devices are rohs compliant p1 1.2 1. modified erase resume from delay 10ms to delay 400us p12,32 jan/17/2006 1.3 1. modified table 15. cfi mode p45,46 apr/24/2006 2. added vlko description p15,18 1.4 1. modified cfi mode p45,46 jul/11/2006 1.5 1. datasheet format changed all a ug/15/2006 1.6 1. data modification all a ug/16/2006 1.7 1. data modification all a ug/17/2006 1.8 1. added statement p44 no v/06/2006 1.9 1. revised statement p14 dec/28/2007 2.0 1. added note 1 into table 3. command definitions p9 jan/17/2008 2.1 1. modified figure 9. ce# controlled write timing waveform p29 feb/21/2008 2.2 1. revised twc, tcwc, tds ac timing spec p20 jul/31/2008
mx29lv040c 44 m acronix i nternational c o., l td . headquarters macronix, int'l co., ltd. 16, li-hsin road, science park, hsinchu, taiwan, r.o.c. tel: +886-3-5786688 fax: +886-3-5632888 macronix america, inc. 680 north mccarthy blvd. milpitas, ca 95035, u.s.a. tel: +1-408-262-8887 fax: +1-408-262-8810 email: sales.northamerica@macronix.com macronix japan cayman islands ltd. nkf bldg. 5f, 1-2 higashida-cho, kawasaki-ku kawasaki-shi, kanagawa pref. 210-0005, japan tel: +81-44-246-9100 fax: +81-44-246-9105 macronix (hong kong) co., limited. 702-703, 7/f, building 9, hong kong science park, 5 science park west avenue, sha tin, n.t. tel: +86-852-2607-4289 fax: +86-852-2607-4229 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. taipei office macronix, int'l co., ltd. 19f, 4, min-chuan e. road, sec. 3, taipei, taiwan, r.o.c. tel: +886-2-2509-3300 fax: +886-2-2509-2200 macronix europe n.v. koningin astridlaan 59, bus 1 1780 wemmel belgium tel: +32-2-456-8020 fax: +32-2-456-8021 singapore office macronix pte. ltd. 1 marine parade central #11-03 parkway centre singapore 449408 tel: +65-6346-5505 fax: +65-6348-8096 macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications.

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